1. Field of the Disclosure
Generally, the present disclosure relates to integrated circuits and methods for the formation thereof, and, more particularly, to integrated circuits including capacitors whose capacitance can be adjusted by applying a voltage thereto.
2. Description of the Related Art
Integrated circuits typically include a large number of circuit elements, in particular field effect transistors. In a field effect transistor, a gate electrode is provided. The gate electrode may be separated from a channel region of the field effect transistor by a gate insulation layer that provides electrical insulation between the gate electrode and the channel region. Adjacent the channel region, a source region and a drain region that are doped to have a different conductivity type than the channel region are provided. Depending on an electric voltage applied to the gate electrode, the field effect transistor may be switched between an ON-state and an OFF-state, wherein an electrical conductivity of the channel region in the ON-state is greater than an electrical conductivity of the channel region in the OFF-state.
In addition to field effect transistors, other circuit elements, such as inductivities, resistors, diodes and capacitors, may be provided in an integrated circuit. Types of capacitors that may be provided in integrated circuits include metal oxide semiconductor capacitors (MOS capacitors). A MOS capacitor may have a configuration similar to that of a field effect transistor, wherein, however, no transitions between regions having a different conductivity type, such as those provided in a field effect transistor between the channel region and the source and drain regions, are provided. The MOS capacitor may include a body region that is provided below a gate electrode of the MOS capacitor and separated therefrom by a gate insulation layer. Adjacent the body region, highly doped semiconductor regions may be provided which are doped to have a same conductivity type as the body region and have a higher dopant concentration than the body region. A first capacitor electrode of the MOS capacitor is provided by the gate electrode, and a second capacitor electrode of the MOS capacitor is provided by the body region. The highly doped semiconductor regions adjacent the body region may be used for providing an electrical connection to the body region by means of contact holes that are formed in an interlayer dielectric above the highly doped semiconductor regions and are filled with an electrically conductive material. An additional contact hole filled with an electrically conductive material may be provided over the gate electrode for providing an electrical connection to the gate electrode.
Types of MOS capacitors include NMOS capacitors, wherein the body region is N-doped, and PMOS capacitors, wherein the body region is P-doped.
A capacitance of a MOS capacitor may be adjusted by varying a gate voltage that is applied between the gate electrode and the body region of the MOS capacitor. The application of the gate voltage may create an electric field in the body region, which may have an influence on the distribution of charge carriers in the body region. Depending on the polarity of the gate voltage, an accumulation or a depletion of majority charge carriers may be obtained in a portion of the body region adjacent the gate insulation layer. In an NMOS capacitor, an accumulation of electrons may be obtained by applying a positive voltage to the gate electrode, and depletion of electrons may be obtained by applying a negative voltage to the gate electrode. In a PMOS capacitor, an accumulation of holes may be obtained by applying a negative voltage to the gate electrode, and a depletion of holes may be obtained by applying a positive voltage to the gate electrode. An accumulation of majority charge carriers may increase the capacity of the MOS capacitor, and a depletion of majority charge carriers may reduce the capacity of the MOS capacitor. Hence, the MOS capacitor may provide a voltage dependent capacitance, thus being a varactor. Herein, the term “varactor” will be used to denote a capacitor whose capacitance can be varied by applying a voltage thereto.
As described above, for using the full tuning range of the capacitance of the MOS varactor, it may be necessary to use both positive and negative gate voltages. For some applications, this may be disadvantageous, and it may be useful to have a device that provides a high tunability of its capacitance by using only one polarity of the gate voltage, which is denoted as “zero referenced tunability.” For this purpose, it has been proposed to form the gate electrode of a MOS varactor from doped polysilicon, wherein the doping of the gate electrode is opposite to the doping of the body region. Accordingly, a P-doped gate electrode may be used in NMOS capacitors, and an N-doped gate electrode may be used in PMOS capacitors. The doping of the gate electrode may have an influence on the Fermi energy of electrons in the gate electrode, which may lead to a bending of the valance band and the conduction band of the semiconductor material of the body region in the vicinity of the gate electrode. The bending of energy bands may have an influence on the distribution of charge carriers in the body region, which may have an influence on the voltage dependency of the capacity of the MOS capacitor similar to that of a bias of the gate voltage. Thus, a zero referenced tunability of the MOS capacitor may be improved.
However, this approach may have some issues associated therewith. For doping the gate electrode of the MOS capacitor differently than the highly doped semiconductor regions adjacent the body region, masks, such as photoresist masks, may be required for blocking dopant ions in ion implantation processes that are used for doping the highly doped semiconductor regions and the gate electrode. In particular, a mask may be formed over the gate electrode when ions of a dopant of a first conductivity type, for example, ions of an N-type dopant in the case of an NMOS capacitor, are implanted into the highly doped semiconductor regions adjacent the gate electrode, and a mask may be formed over the highly doped semiconductors when ions of a dopant of a second conductivity type, for example, ions of a P-type dopant in the case of a PMOS capacitor, are implanted into the gate electrode. In order to avoid an inadvertent doping of the highly doped semiconductor regions and/or the gate electrode with dopants of the wrong conductivity type, it has been proposed to form shallow trench isolations below the sidewalls of the gate electrode. Thus, a relatively complex manufacturing process may be required for forming a MOS capacitor having a relatively high zero referenced tunability.
In view of the situation described above, the present disclosure provides semiconductor structures and varactors that may help to substantially avoid or at least reduce the above-mentioned problems, and methods for the formation of such semiconductor structures and varactors.